1. Field of the Invention
This invention relates to a system and method to compensate for the difference in timing for positive and negative signal transitions, particularly for use in conjunction with automatic test equipment.
2. Brief Description of the Prior Art
Semiconductor testers are collections of circuits which generate various waveforms designed to stimulate a semiconductor device under test (DUT) so that the outputs of the DUT for the various stimuli can be measured. The stimuli and measurement references have timing associated therewith which must be very precise.
The total timing accuracy of automatic test equipment is determined by the ability of calibration procedures to compensate for timing errors that cannot be corrected or avoided in the inherent design or manufacturing process. The total system timing error is comprised of different error components from various error sources in the equipment. This timing error determines the accuracy to which the tester is capable of generating digital inputs to the device under test (DUT) and the accuracy to which the tester is able to monitor the digital response of the DUT. Tester calibration procedures are designed to isolate and measure each error component. During actual device testing, these error measurements are used to adjust programmed timing values to compensate for the error sources.
Adequate functional testing of digital devices at specified performance limits generally requires the tester timing accuracy to be within 2% of the rate of operation of the DUT. As the rate of operation of devices increases, the timing accuracy of the tester becomes a larger percentage of the cycle time. Tester timing accuracy has traditionally struggled to keep pace with device performance, resulting in testing compromises or increasingly more complex test procedures.
One of the timing error sources in a tester is associated with the positive and negative signal transitions through the digital stimulus and response measurement circuitry. For example, if the tester is programmed to provide a digital pulse as an input to the DUT, the programmed width of the pulse will be in error due to differences in positive and negative transition timing of the signal generator. Similarly, if the tester measures a digital pulse response of a DUT, the measurement of the pulse will be in error due to differences in the manner of measurement circuitry response to positive and negative transitions. The tester calibration procedure must measure the differences between positive and negative signal generator outputs and measurement circuit response thereto. The accuracy to which the tester can measure this error determines the resulting contribution of this error source to the total timing error of the system.
One method of reducing this timing error component is to adjust or "trim" the stimulus and measurement circuitry as a manufacturing process step. The advantage of this method is that the error source is measured and compensated for once during manufacturing and does not require inclusion in the periodic tester calibration process. There are two key disadvantages to this method. First, this method is usually a manual adjustment and, therefore, not only adds to manufacturing cost, but also introduces the possibility of human error. Second and more important, if the parameters of the stimulus/response circuitry change with time, temperature or damage, the resulting timing error may be significantly greater since it is not practical to readjust the compensation to take such changes into account.
Most other methods of reducing this timing error component involve a periodic calibration process that uses calibration references to measure the error. The accuracy of the measurement is determined by the accuracy of the calibration references used. The calibration process usually involves one of several variations of the following basic process:
1. Generating a reference signal with a known timing relationship between a positive and negative transition using a reference signal generator.
2. Measuring the positive and negative transitions of the signal with the response measurement circuitry of the tester (on the tester channel being calibrated).
3. Determining the difference between the known timing relationship of the reference positive and negative transitions and the measured positive and negative transitions. This represents the transition dependent error of the response measurement circuitry.
4. Generating a signal with an assumed timing relationship between a positive and negative transition using the digital stimulus generator of the tester channel being calibrated.
5. Measuring the positive and negative transitions using either a calibrated tester response measurement circuit or a reference response measurement circuit.
6. Determining the difference between the assumed timing relationship of the positive and negative transitions of the signal and the timing relationship actually measured with the calibrated response measurement circuit or reference response measurement circuit. This represents the transition dependent error of the digital stimulus generator circuitry.
The accuracy of these measurements and therefore the resulting capability of the calibration process to reduce the transition dependent errors is directly affected by the accuracy and stability of the reference signal generator and/or reference response measurement circuit. Typical configurations for reference circuits are generally solid state electronic circuits that are characterized and adjusted as a manufacturing procedure to provide accurate performance. The problems with present calibration methods using the above described types of calibration references are:
1. The characteristics and performance of the references can change with time and environmental conditions, thus affecting the stability of the references.
2. The actual characterization and adjustment of the references introduces error.